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Microchip Fabrication 5th Ed By Peter Van Zant.pdf

4. Packaging 5. Final and electrical test In the rst stage,material preparation (see Chapter 2), the raw semiconductingmaterials are mined and puried to meet semiconductor standards. Forsilicon, the starting material is sand, which is converted to puresilicon with a polysilicon structure (Fig. 1.20a). In stage two,the material is formed into a crystal with specic electrical andstructural parameters. Next, thin disks called wafers are cut fromthe crystal and surface treated (Fig. 1.20b) in a process calledcrystal growth and wafer preparation (see Chapter 3). The industryalso makes devices and circuits from germanium and compounds ofdifferent semiconductor materials. In stage three (Fig. 1.20c),wafer fabrication, the devices or integrated circuits are actuallyformed in and on the wafer surface. Up to several thousandidentical devices can be formed on each wafer, although two tothree hundred is a more common number. The area on the waferoccupied by each discrete device or integrated circuit is called achip or die. The wafer fabrication process is also calledfabrication, fab, chip fabrication, or microchip fabrication. Whilea wafer fabrication operation may take several thousand individualsteps, there are two major activities. In the front end of the line(FEOL), the transistors and other devices are formed in the wafersurface. In the back end of the line (BEOL), the devices are wiredtogether with metallization processes, and the circuit is protectedwith a nal sealing layer. Following wafer fabrication, the devicesor circuits on the wafer are complete, but untested and still inwafer form. Next comes an electrical test (called wafer sort) ofevery chip to identify those that meet customer specications. Wafersort may be the last step in the wafer fabrication or the rst stepin the packaging process. Packaging (Fig. 1.20d) is the series ofprocesses that separate the wafer into individual die and placethem into protective packages. This stage also includes nal testingof the chip for conformance to customer specications. The industryalso refers to this stage as assembly and test (A/T). A protectivechip package is necessary to protect the chip from contaminationand abuse, and to provide a durable and substantial electrical leadsystem to allow connection of the chip onto a printed circuit boardor directly into an electronic product. Packaging takes place in adifferent department of the semiconductor producer and quite oftenin a foreign plant. The vast majority of chips are packaged inindividual packages. But a growing percentage are beingincorporated into hybrid circuits, in multichip modules (MCMs), ormounted directly on printed circuit

microchip fabrication 5th ed by peter van zant.pdf

was being somewhat hampered by mask-caused defects and thedamage inicted on the wafers by the contact aligners. The mask andaligner defect problem was solved with the development of the rstpractical projection aligner by Perkin and Elmer Company. Thedecade also saw the improvement of cleanroom construction andoperation, the introduction of ion implantation machines, and theuse of e-beam machines for high-quality mask generation, and masksteppers began to show in fab areas for wafer imaging. Automationof processes started with spin/bake and develop/bake systems. Themove from operator control to automatic control of the processesincreased both wafer throughput and uniformity.20 Once theprocesses were integrated into the equipment, the stage was set fordissemination throughout the world. Along with the processimprovements came a more detailed understanding of the physics ofsolid-state devices, which allowed the mastering of the technologyby student engineers worldwide. The focus in the 1980s wasautomation of all phases of wafer fabrication and packaging andelimination of operators from the fab areas. Automation increasesmanufacturing efciency, minimizes processing errors, and keeps thewafer fabrication areas cleaner by limiting the number ofoperators, who are one of the major sources of contamination in theprocess. These issues are examined in more detail in Chapter 4. Onefeature of automation is exibility. As in automobile industryautomation, especially in the area of design, manufacturers beganto design more complicated chips. The new designs, in turn,presented new manufacturing challenges that led to the developmentof new processes. At these sophisticated levels, machine automationis required to achieve the process control and repeatability. The1980s started with American and European dominance and ended as aworldwide industry. Through the 1970s and 1980s, the onemicronfeature size barrier loomed as both opportunity and challenge. Theopportunity was a new era of megachips with vastly increased speedsand memory. The challenge was the limitations of conventionallithography, additional layers, more step height variation on thewafer surface, and increasing wafer diameters, to mention a few.The onemicron barrier was crossed in the early 1990s when 50percent7 of microchip fabrication lines were working at the micronor submicron level. The industry matured into more traditionalfocuses on manufacturing and marketing issues. Early on, the protstrategy was to ride the innovation curve. That meant always beingrst (or close to rst) with the latest and greatest chip that couldbe sold with enough prot to pay for the R&D and nance newdesigns. The prot potential of this

insulator (SOI) such as sapphire, and silicon on diamond (SOD).Diamond dissipates heat better than silicon. Another structure is alayer of strained silicon deposited on a wafer ofsilicon-germanium. Strained silicon occurs when silicon atoms aredeposited on a Si/Ge (sSOI) layer previously deposited on aninsulator. Si/Ge atoms are more widely spaced than normal silicon.During the deposition, the silicon atoms stretch to align to theSI/Ge atoms, staining the silicon layer. The electrical effect isto lower the silicon resistance, allowing electrons to move up to70 percent faster. This structure brings performance benets to MOStransistors (see Chapter 16). Ferroelectric Materials In theongoing search for faster and more reliable memory structures,ferroelectrics have emerged as a viable option. A memory cell muststore information in one of two states (on/off, high/low, 0/1), beable to respond quickly (read and write), and be capable ofchanging states reliably. Ferroelectric material capacitors such asPbZr1x Tx O3 (PZT) and SrBi2 Ta2 O9 (SBT) exhibit these desirablecharacteristics. They are incorporated into SiCMOS (see Chapter 16)memory circuits known as ferroelectric random access memories(FeRAMs).5 Diamond Semiconductors Moores law cannot go indenitelyinto the future. One end point is when the transistor parts becomeso tiny that the physics governing transistor action no longerwork. Another limit is heat dissipation. Bigger and denser chipsrun very hot. Unfortunately, high heat also degrades the electricaloperations and can render the chip useless. Diamond is a crystalmaterial that dissipates heat much faster than silicon. Despitethis positive aspect, diamond as a semiconductor wafer has facedbarriers of cost, uniformity, and nding a supply of large diamonds.However, there is new research into making synthetic diamonds usingvapor deposition techniques. Doping diamond is the next barrier.This material is being explored and may nd its way into fabricationareas of the future.6 Process Chemicals It should be fairly obviousthat extensive processing is required to change the rawsemiconducting materials into useful devices. The majority of theseprocesses use chemicals. In fact, microchip fabrication isprimarily a chemical process or, more correctly, a series ofchemical


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